The present invention pertains to a driving circuit, for example, a current output type driving circuit used in a bubble jet printer for supplying a driving current to heat a printer head part.
At a head part of a bubble jet printer, a current is supplied to a heater to generate heat, and bubbles of ink are created in the nozzle of the header part by the heat and sprayed onto a paper surface. Usually, a driver circuit is provided at the head part in order to supply the current to the heater. In the past, the driver circuit was configured using bipolar transistors.
FIG. 6 is an outlined diagram showing an example configuration of the driving circuit. As shown in the figure, the driver circuit is configured with input buffer 10, level conversion circuit 20, driver part 30, and current output part 40. In terms of normal operating speed, when the driving circuit shown in FIG. 6 is configured using CMOS transistors inferior to bipolar transistors, operating speed, in particular, specification of the output current characteristic at current output part 40, becomes important.
Ideally, it is desirable if the driving current supplied to the heater by the driving circuit can be controlled through the input of control signal Sin without any distortion. That is, the waveform of the driving current supplied to the heater needs to match roughly the waveform of control signal Sin. However, when the driving circuit is actually configured using CMOS transistors, the waveform of the driving current output may differ from the waveform of input signal Sin due to frequency characteristics and delay characteristics of the circuit.
FIG. 7 shows waveform diagrams showing example waveforms of input signal Sin and driving current IH output from the driving circuit. As shown in the figure, rising time tR, falling time tF, rise delay time tPLH, and fall delay time tPHL in the waveform of driving urrent IH are of important specifications.
Rising time tR refers to the time required for driving current IH to go from 10% to 90% of maximum current value IHmax, and falling time tF refers to the time required for driving current IH to fall from 90% to 10% of maximum current value IHmax. In addition, rise delay time tPLH refers to the time the rising edge of the driving current is delayed from the rising edge of input signal Sin, and fall delay time tPHL refers to the time the falling edge of the driving current is delayed from the falling edge of input signal Sin.
FIG. 8 shows drain-source voltage Vds and drain current Ids characteristics of current output MOS transistor QH used for output part 40. The resistance of a MOS transistor when it is conductive, or so-called on-resistance, is determined by its gate-source voltage Vg, and the on-resistance of the MOS transistor depends only on its gate-source voltage Vg, not drain-source voltage Vds, except in saturated regions. In addition, drain current Ids of the MOS transistor, that is, driving current IH supplied to load resistor R1, is determined based on source voltage VH, load resistance value r1, and on-resistance rON of the MOS transistor and is given by the following equation.
Equation 1
IH=VH/(r1+rON)xe2x80x83xe2x80x83(1)
The dotted line in FIG. 8 indicates the load characteristic of the heater connected to the drain of the MOS transistor. Here, assume that source voltage VH is 25V, and the resistance value of the heater is approximately 250xcexa9.
As shown in FIG. 8, driving current IH supplied to the heater changes from 0 mA to approximately 100 mA according to gate voltage Vg of the transistor.
The characteristics of gate voltage Vg of current output transistor QH and output current IH thereof with respect to input signal Sin can be obtained based on the output characteristic and load characteristic of the MOS transistor for current output.
FIG. 9 shows respective waveforms of input signal Sin, gate voltage Vg of current output transistor QH, and driving current IH. In addition, in FIG. 9, the relationship between rise delay time tPLH and fall delay time tPHL is also shown. As shown in FIG. 9, when the voltage is half the maximum value, for example, when the maximum value is the source voltage for input buffer 10, that is, Vdd=5V, at the rising edge of input signal Sin, rise delay time tPLH refers to the delay time from when it has reached half of said value, that is, 2.5V, until gate voltage Vg of current output transistor QH reaches 6V, for example. Furthermore, here, assume that the maximum value of gate voltage Vg of transistor QH is approximately equal to source voltage VH, for example, 25V.
In addition, fall delay time tPHL refers to the time from when the voltage has reached half of maximum value Vdd, that is, 2.5V, at the falling edge of input signal Sin until gate voltage Vg of transistor QH drops to 6V.
In addition, rise delay time tPLH is approximately equal to the delay time from when input signal Sin has reached half the maximum value until driving current IH reaches half the maximum value. On the other hand, fall delay time tPHL is approximately equal to the delay time from when input signal Sin has reached half the maximum value until driving current IH reaches half the maximum value.
As shown in the figure, the time required for gate voltage Vg of current output transistor QH to rise from 0V to 6V is less than the time required for gate voltage Vg to fall from the maximum value of 25V to 6V. That is, fall delay time tPHL greater than rise delay time tPLH.
Accordingly, when rising time tR and falling time tF of driving current IH to be output are made equal, fall delay time tPHL of driving current IH becomes longer than rise delay time tPLH with respect to input signal Sin. That is, the balance between the rise and the fall of driving current IH deteriorates, and pulse width TW-IH of driving current IH becomes greater than pulse width TW-IN of input signal Sin, so that driving current IH can no longer be controlled highly accurately.
The conventional driving circuit adopted a method that sets a short falling time in order to improve driving current controllability.
For example, as shown in FIG. 10, the times required for gate voltage Vg of current output transistor QH to start changing after input signal Sin becomes half the maximum value at the rising edge and the falling edge of input signal Sin are denoted as T11 and T21, respectively, and set as T11=T21=10 ns. Furthermore, rising time TR and falling time TF of driving current IH of transistor QH are set as TR=TF=20 ns.
As shown in FIG. 10, time T12 required for gate voltage Vg to rise to 6V is roughly xc2xc of rising time TR, and time T22 required for gate voltage Vg to fall from the maximum value of 25V to 6V is roughly xc2xe of falling time TF. That is, T12=5 ns, and T22=15 ns. Thus, rise delay time TPLH and fall delay time TPHL are obtained as follows, respectively. That is, TPLH=T11+T12=15 ns, and TPHL=T21+T22=25 ns. Accordingly, the difference between rise delay time TPLH and fall delay time TPHL is TPLHxe2x88x92TPHL=10 ns. For example, when pulse width Tw-in of input signal Sin is 100 ns, pulse width TW-IH of driving current IH becomes roughly 110 ns, creating a difference between the input and the output pulse widths, so that the timing of the driving current can not be controlled accurately.
Conventionally, a method for reducing falling time TF of driving current IH has been used in order to reduce fall delay time TPHL. However, said method is disadvantageous in that not only the symmetry between rising time TR and falling time TF is destroyed, but ringing also increases as undershoot increases at the falling edge of driving current IH when falling time TF is too short.
The present invention was developed in light of such a situation, and its objective is to present a driving circuit by which the fall delay time can be reduced while reducing the ringing during a transition period of the output current, and the output timing of the driving current can be controlled highly accurately.
In order to achieve the aforementioned objective, the driving circuit of the present invention has a level conversion circuit which converts a first logical level signal into a second logical level signal having a higher logical amplitude than that of the aforementioned first logical level signal and a driver part which outputs a driving signal according to a signal output from the aforementioned level conversion circuit, wherein the aforementioned driver part has a first MOS transistor connected between a first power source potential and an output terminal, a second MOS transistor connected between the aforementioned output terminal and a second power source potential which becomes conductive to complement the aforementioned first MOS transistor, a first diode circuit connected between the aforementioned output terminal and the aforementioned second MOS transistor, and a first resistor connected in parallel with the aforementioned first diode circuit.
In addition, in the present invention, it is desirable when the aforementioned driver part has a second diode circuit connected between the aforementioned first MOS transistor and the aforementioned output terminal and a second resistor connected in parallel with the aforementioned second diode circuit.
In addition, it is desirable when the aforementioned first diode circuit has a third diode-connected MOS transistor, and when the aforementioned second diode circuit has a fourth diode-connected MOS transistor.
Furthermore, it is desirable when the aforementioned first MOS transistor is a PMOS transistor, and the aforementioned second and the third MOS transistors are nMOS transistors.